Generally, serial data communication includes a transmitter and a receiver. The transmitter employs one or more internally generated high speed clocks to multiplex the data into a serial data stream that is then placed on a communication media. The serial data stream travels on the communication media and is then obtained from the media by the receiver. The serial data stream is then processed by the receiver in order to recover the original data. The receiver employs one or more internal generated high speed clocks in order to sample and recover the original data.
The duty cycle of these clocks is an important component in reducing timing error induced and maintaining a suitable level of bit error rate (BER) required by some communication standards especially when Half-Baud-Rate (HBR) clocks are used. Even though HBR clocks provide power advantage over their Full-Baud-Rate (FBR) counterpart, deviation from a desired duty cycle (e.g., fifty percent) increases ambiguity in data boundaries during transmission and re-sampling, and thus increases the probability of error. Furthermore, as serial communication speeds continue to increase to well over a Gigabit per second, duty cycle errors/distortions can become even more problematic.
What is needed are systems and methods that facilitate serial communication by detecting and correcting duty cycle errors/distortions in a relatively efficient manner.